Complementary metal-oxide-semiconductor (CMOS) technology is a dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has provided significant improvement in the speed performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced when CMOS devices are scaled into the sub-100 nm regime. An attractive approach for additional improvement of CMOS transistor performance exploits strain-induced band-structure modification and mobility enhancement to increase the transistor drive current. Enhanced electron and hole mobilities in silicon (Si) under biaxial tensile strain can be achieved. Enhanced electron and hole mobilities improve the drive currents of N-channel and P-channel MOSFETs, respectively. In the strained silicon, electrons experience less resistance and flow up to 70 percent faster, which can lead to chips that are up to 35 percent faster without having to further shrink the size of transistors.
As shown in FIG. 1A, many designs of strained silicon layers for transistor fabrication utilize buffer layers or complex multi-layer structures on a bulk silicon substrate 20. Strained silicon substrate technology often utilize a silicon-germanium (SiGe) graded buffer layer 22 with a thickness in the order of microns. A relaxed SiGe layer 24 overlies the graded buffer layer 22. The relaxed SiGe layer 24 has a larger natural lattice constant than that of silicon. Relaxed crystalline silicon is said to be lattice-mismatched with respect to relaxed crystalline SiGe due to the difference in their lattice constants. As a result, a thin layer of silicon 26 that is epitaxially grown on the relaxed SiGe layer 24 will be under biaxial tensile strain because the lattice of the thin layer of silicon 26 is forced to align to the lattice of the relaxed crystalline SiGe layer 24, as illustrated in FIGS. 1B and 1C. Referring again to FIG. 1A, a transistor 28 is formed in the silicon layer 26. The transistor 28 includes a source 30, a drain 32 and a gate 34. Transistors fabricated on the strained silicon layer 26 will have enhanced electrical performance. As also shown in FIG. 1A, the transistor 28 is typically bounded by an isolation region 36 (e.g., shallow-trench isolation (STI), local oxidation of silicon (LOCOS), field oxide (FOX)).
The graded SiGe buffer layer 22 introduces a lattice mismatch with the underlying silicon substrate 20, which may result in a dispersed, three-dimensional misfit dislocation network. Strain-relieving glide of threading dislocations 38 is facilitated. Dislocations formed in the graded buffer layer 22 may propagate to the wafer surface, resulting in a defect density in the order of 104–105 defects per cm2. Such a high defect density may present a significant barrier for the production of integrated circuits using such substrates. Also, the underlying strain fields of the misfit arrays result in a characteristic cross-hatch surface roughness. This surface roughness can be a significant problem as it potentially degrades channel mobility in active devices. Hence, there is a need for a way to reduce defect density for such strained silicon substrate structures.